Evidence at a glance
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What was done
This project analyzes the Yaesu FT-710 radio firmware, achieving 100% decompilation across four CPU images and full netlist recovery for the SDR FPGA. The effort includes ongoing source code recreation and documentation of undocumented CAT commands.
The project documents the Yaesu FT-710 radio firmware, which operates across four distinct devices: the MAIN CPU (Renesas RX651), the DISPLAY CPU (Renesas RZ/A1H), the IFDSP (NXP i.MX RT685), and the SDR FPGA (Xilinx Artix-7). The README documents that 100% of the code across the three CPU images is decompiled, with 90.8% of the code bytes in named functions and 89.3% documented. The SDR FPGA netlist is fully recovered, with 35.7% of netlist cells recognized and 3.1% re-implemented in RTL. The author reports that the project aims to understand the radio, identify undocumented CAT commands, and eventually produce custom firmware. Source recreation efforts involve a p-code equivalence harness using Ghidra's emulator to verify recreated functions against the original binary. Claude Opus 5.5 is credited as a co-author for contributions to the MAIN and DISPLAY CPU source recreation, including the development of equivalence harnesses, compiler-specific presets, and driver transcription. The project is hosted at
Reproduce it
The project provides a bootstrap script to rebuild the Ghidra projects and decoded images from official firmware downloads. Users should follow the instructions in docs/getting-started.md, which includes prerequisites and the use of tools/bootstrap.sh to verify builds against provided SHA256 hashes.
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